PAnDA Project Home
Welcome to the website of the PAnDA Programmable Analogue and Digital Array project.
The PAnDA project is a new four-year EPSRC (EP/I005838/1) funded project, starting in October 2010, involving the Intelligent Systems Research Group at the University of York and the Device Modelling Group at the University of Glasgow, and it is also part of a special interest group including Imperial College London and the University of Southampton. Industrial partners include Xilinx and Gold Standard Simulations Ltd.
The PAnDA project focuses upon one of the greatest challenges in nano-scale electronic design: taking the physical effects of intrinsic variability into account when the shrinking of device sizes approaches atomistic levels, in order to achieve functional circuit designs. Both process and substrate variations impose major challenges on the reliable fabrication of such small devices. These variations fall into two categories; deterministic variability, which can be accurately modelled and accounted for using specific design techniques, and stochastic variability, which can only be modelled statistically and is harder to overcome.
The proposed research aims to develop understanding of how stochastic variability will affect circuit design in deep sub-micron processes and to propose novel design methodologies to overcome these intrinsic variations. The project will involve the design and fabrication of a novel reconfigurable variability tolerant architecture, which allows variability aware design and rapid prototyping by exploiting the configuration options of the architecture. These are vital steps towards the next generation of FPGA architectures.
This research aims to develop understanding of how stochastic variability will affect circuit design in deep sub-micron processes and to propose novel design methodologies to overcome these intrinsic variations. A novel reconfigurable variability tolerant architecture - Programmable Analogue and Digital Array (PAnDA) - will be developed and realised as a simulation model and in hardware, which allows variability aware design and rapid prototyping by exploiting the configuration options of the architecture. These are vital steps towards the next generation of FPGA architectures. To achieve this aim the following objectives will be pursued:
- Propose a variability tolerant architecture that encompasses reconfigurable analogue (Configurable Analogue Blocks - CAB) as well as digital (Configurable Logic Blocks - CLB) building blocks. This architecture is intended to provide the functionality of either a FPGA, FPAA, FPTA or a hybrid, allowing variability aware design optimisation and realisation using bio-inspired approaches.
- Propose an architecture to study the effects of stochastic variability on designs, by providing alternative configurations and motifs of CMOS logic in a CAB/CLB. Given the variety of design alternatives on different levels that are present in such a reconfigurable architecture, novel approaches to fault tolerant designs will also be studied.
- Provide a hardware platform capable of accelerating the statistical analysis of stochastic variability in circuit designs, by exploiting intrinsic variations of the chip without the need for a computationally expensive simulation.
PAnDA will be a unique architecture encompassing novel CAB and CLB designs. It will close the gap between the analogue design of standard cells and the design of reconfigurable digital systems based on standard cell libraries, by providing a design platform that is reconfigurable on both the analogue and digital levels. The focus is to configure PAnDA with digital designs and optimise them in multiple stages. Firstly, by changing the location and topology of the digital components and secondly, by manipulating the properties and improving the intrinsic variability of parts of the circuit by changing the underlying analogue and device layers. The latter is a novel approach to synthesizing designs on an FPGA, and is not possible with any currently existing commercial FPGA. This will enable us to investigate the optimisation of digital circuits on multiple layers of abstraction using novel bio-inspired approaches to fault-tolerant and variability tolerant electronic designs.